This invention relates to a semiconductor device such as a nonvolatile memory or a MOS transistor and a method of manufacturing the semiconductor device, and in particular to a flash EEROM and a method of manufacturing the same.
In recent years, there are increasing demands for the higher integration, improved performance and lower power consumption of a semiconductor device. It is very important for meeting these demands to make thinner the gate insulator film of a MOS transistor or the insulator film of a memory cell such as a nonvolatile memory. In order meet this requirement for thinning the gate insulator film, etc., an improvement on the method of manufacturing the gate insulator film or the gate electrode has become necessary.
FIGS. 1A to 1H are cross-sectional views illustrating the method of manufacturing the memory cell portion of a flash EEPROM representing the conventional nonvolatile memory. In the followings, the same constitutional component will be identified by the same reference numeral, thereby omitting the repetition of explanation thereof.
As shown in FIG. 1A, first of all, a field oxide film (not shown) is formed on, for example, a p-type silicon substrate 1 for the purpose of isolation by making use of a selective oxidation method. Then, as shown in FIG. 1B, a silicon dioxide film 2 having a thickness of 10 nm is formed on the silicon dioxide substrate 1 by making use of a thermal oxidation method. This silicon dioxide film 2 is intended to be used as a first gate oxide film or a so-called tunnel oxide film in general.
Then, as shown in FIG. 1C, a polycrystalline silicon film 3 having a thickness of 200 nm and containing phosphorus as an impurity is formed on the silicon dioxide film 2 by making use of the LPCVD method. This polycrystalline silicon film 3 is intended to be used as a first gate electrode or a so-called floating gate in general.
Then, as shown in FIG. 1D, a silicon dioxide film 4, a silicon nitride film 5 and a silicon dioxide film 6, each having a thickness of 6 nm, are successively formed on the floating gate 3 by making use of the LPCVD method. The insulator film having this three-layered structure is intended to be used as a second gate insulator film or a so-called inter-poly insulator film or a so-called ONO film in general.
Thereafter, as shown in FIG. 1E, a polycrystalline silicon film 8 containing phosphorus as an impurity is formed on the ONO film 7 by making use of the LPCVD method. This polycrystalline silicon film 8 is intended to be used as a second gate electrode or a so-called control gate in general.
Further, as shown in FIG. 1F, a photoresist 9 is coated on the control gate 8 and then worked into a desired pattern by making use of a photoengraving method. Subsequently, as shown in FIG. 1G, the control gate 8, the ONO film 7 and the floating gate 3 are successively etched perpendicularly by means of a dry etching method such as an RIE (Reactive Ion Etching) method with the photoresist 9 being employed as a mask. In this occasion, the silicon dioxide film 2 functions as an etching stopper when the floating gate 3 is etched.
Then, as shown in FIG. 1H, a photoresist 9 is removed. Thereafter, as shown in FIG. 2A, a silicon dioxide film 10 is formed by means of a thermal oxidation method for the purposes of suppressing a leak current at the gate terminal, improving the surface breakdown voltage of peripheral circuit MOS transistor of high breakdown voltage, i.e. the breakdown voltage of the gate insulator film, and recovering from a damage that might be introduced via the gate electrode into the gate oxide film at the occasion of the RIE etching. This oxidation process is generally called a post-oxidation process, and the silicon dioxide film 10 formed in this process is called a post-oxide film.
Subsequently, source/drain regions (not shown) are formed by way of ion implantation using an impurity, and, in subsequent to the deposition of an insulator film (not shown) and formation of openings, predetermined wirings (not shown) are formed thereon, thus forming the memory cell portion of the EEPROM.
In the followings, problems associated with this conventional manufacturing method of the memory cell will be explained.
First of all, oxygen, etc. functioning as an oxidant may be diffused from the oxide films 4 and 6 of the ONO film 7, thereby oxidizing the polycrystalline silicon film of the control gate 3 and the floating gate 8. Specifically, the gate terminal of the ONO film 7 is excessively oxidized, thus increasing the thickness of oxide film as indicated for instance by the reference numeral 11 in FIGS. 2A and 2B. This swollen oxide film portion 11 which is formed at the gate terminal is generally called a gate bird's beak.
This gate bird's beak invites an increase in effective film thickness of the inter poly-insulator film 7, and since it is difficult to control the manner of formation of the gate bird's beak, it will give rise to non-uniformity in film thickness of the inter poly-insulator film 7 between the memory cells.
Moreover, as shown in FIG. 2A, as the gate length 12 becomes shorter due to an increased fineness of the memory cell, the ratio of the gate bird's beak length 11 to the gate length 12 becomes larger. Therefore, the influence of the gate bird's beak will become more prominent as the fineness of memory cell is further advanced, so that any attempt to make the inter-poly insulator film 7 thinner will be substantially hindered.
Further, since the silicon dioxide film formed by means of the CVD method is poor in the effect of inhibiting the diffusion of oxidant as compared with the silicon dioxide film formed by means of thermal oxidation method, the gate bird's beak will creep more prominently and deeply in the inter-poly insulator film 7.
Usually, the writing and erasing of data to a memory cell are effected at first by distributing the voltage impressed onto the control gate 8 by the ratio between the capacity of the capacitor constituted by the substrate 1, the tunnel oxide film 2 and the floating gate 3 and the capacity of the capacitor constituted by the floating gate 3, the inter-poly insulator film 7 and the control gate 8, and then by impressing thus distributed voltage onto the inter-poly insulator film 7. Therefore, if the film thickness of the inter-poly insulator film 7 is increased due to the aforementioned post-oxidation, or the film thickness of the inter-poly insulator film 7 is non-uniform, the writing and erasing characteristics of the memory cell will be deteriorated or fluctuated.
Furthermore, if the gate terminal of the inter-poly insulator film 7 is oxidized, the growth of crystal grain of the polycrystalline silicon constituting the floating gate 3 and the control gate 8 is promoted. As a result, the shape of gate electrodes of the floating gate 3 and the control gate 8 would be deformed, thus giving rise to a local concentration of electric field in the inter-poly insulator film 7. As a result, the reliability of the insulator film would be deteriorated, or under some circumstance, it may give rise to a defective insulator film, thus deteriorating the yield of memory cell.
FIG. 3 is a graph illustrating the distribution of breakdown voltage of the ONO film before and after the post-oxidation. It will be seen from FIG. 3 that when the post-oxidation is performed, the distribution of breakdown voltage of the ONO film is enlarged and at the same time the breakdown voltage is lowered.
In the foregoing, the problem of gate bird's beak in the inter-poly insulator film 7 has been mainly discussed. However, a bird's beak similar to that mentioned above may also be generated in the tunnel oxide film 2 due to the post-oxidation, thereby causing an increase in film thickness or the non-uniformity of film thickness of the tunnel oxide film 2, thus deteriorating the characteristics of the memory cell.
Furthermore, it is impossible with the aforementioned conventional manufacturing method to perform the en bloc working of the gates of the memory cell portion and peripheral circuit transistor portion of the flash EEPROM.
FIGS. 4A to 4J and FIGS. 5A to 5J illustrate the manufacturing process for simultaneously working the gates of the memory cell portion and the peripheral circuit transistor portion, and problems involved in this manufacturing process. Specifically, FIGS. 4A to 4J show the cross-sections of the memory cell portion in the manufacture thereof; while FIGS. 5A to 5J show the cross-sections of the peripheral circuit portion in the manufacture thereof.
First of all, a field oxide film (not shown) for isolation is formed on a p-type silicon substrate 1 by making use of a selective oxidation method. Then, as shown in FIGS. 4A and 5A, a silicon dioxide film 13 having a thickness of 20 nm is formed on the silicon dioxide substrate 1 by making use of a thermal oxidation method. Subsequently, a photoresist 14 is coated on the silicon dioxide film 13 and then a portion of the photoresist 14 that has been coated on the memory cell portion is removed by making use of a photoengraving method.
Thereafter, as shown in FIGS. 4B and 5B, a portion of silicon dioxide film 13 that has been coated on the memory cell portion is selectively removed by means of a wet etching method with the photoresist 14 being used as a mask, and then the photoresist 14 is also removed.
Then, as shown in FIGS. 4C and 5C, a silicon dioxide film 2 having a thickness of 10 nm is formed by means of a thermal oxidation method. In this step, the film thickness of the silicon film 13 which has been formed in advance at the peripheral circuit portion is increased. The silicon dioxide film 2 is intended to be employed as a tunnel oxide film of the memory cell portion, while the silicon dioxide film 13 is intended to be employed as a gate oxide film of the peripheral circuit transistor.
Then, as shown in FIGS. 4D and 5D, a polycrystalline silicon film 3 having a thickness of 200 nm and containing phosphorus as an impurity is formed on the silicon dioxide film 2 by making use of the LPCVD method. This polycrystalline silicon film 3 is intended to be used as a floating gate in general. Then, an ONO film 7 comprising a silicon dioxide film 4, a silicon nitride film 5 and a silicon dioxide film 6 is formed on the floating gate 3 by making use of the LPCVD method. Thereafter, a photoresist 15 is formed on the ONO film 7 and a portion of which has been formed on the peripheral circuit transistor is removed by making use of a photo-engraving method.
Thereafter, as shown in FIGS. 4E and SE, a portion of ONO film 7 that has been formed on the peripheral circuit transistor portion is selectively removed by means of the RIE method with the photoresist 15 being used as a mask, and then the photoresist 15 is also removed.
Then, a polycrystalline silicon film 8 having a thickness of 300 nm and containing phosphorus as an impurity is formed all over the surface by means of the LPCVD method. At the memory portion, this polycrystalline silicon film 8 is formed on the ONO film 7 and functions as a control gate. At the peripheral transistor portion, the polycrystalline silicon film 8 is formed on the polycrystalline silicon film 3, and these polycrystalline silicon films 3 and 8 are used as the gate electrode of a MOS transistor.
Further, as shown in FIGS. 4F and 5F, a photoresist 16 is coated on the polycrystalline film 8, and then the portions of the photoresist 16 that have been formed on the memory cell portion and the peripheral circuit transistor portion are worked respectively into a desired pattern by means of a photo-engraving method.
Then, the polycrystalline film 8 is subjected to etching by means of the RIE method with the photoresist 16 being used as a mask. In this RIE, an etching gas having an selective etching property, i.e. an etching gas which is capable of etching silicon but incapable of etching silicon dioxide film and silicon nitride film is employed. In this etching process, the ONO film 7 acts as an etching stopper in the memory cell portion as shown in FIG. 4G. Whereas, in the peripheral circuit transistor portion, since the ONO film is not existed as shown in FIG. 5G, the polycrystalline silicon film 3 is also etched so that the silicon dioxide film 13 acts as an etching stopper.
Furthermore, as shown in FIG. 4H, a portion of the ONO film 7 which is formed in the memory cell portion is etched by means of the RIE method employing an etching gas which is capable of etching silicon dioxide film and silicon nitride film but incapable of etching silicon.
Since the oxide film 13 is exposed in the peripheral circuit transistor portion in this etching step, the oxide film 13 is etched as shown in FIG. 5H, thus exposing the substrate 1. FIG. 5H shows a cross-section of the peripheral circuit transistor portion at this step.
Subsequently, the polycrystalline silicon film 3 is selectively and perpendicularly etched by means of the RIE method employing an etching gas which is capable of etching silicon but incapable of etching silicon dioxide film. In this etching process, the silicon dioxide film 2 acts as an etching stopper in the memory cell portion as shown in FIG. 4I.
Since the silicon substrate 1 is exposed in the peripheral circuit transistor portion in this etching step as shown in FIG. 5I, the silicon substrate 1 is etched.
Subsequently, as shown in FIGS. 4J and 5J, a photoresist 16 is removed.
If the gate electrodes of the memory cell portion and the peripheral circuit transistor portion are formed en bloc, a portion of the silicon substrate located beside the gate electrode in the peripheral circuit transistor portion is etched so that it is impossible to actuate the transistor of the peripheral circuit normally. Because of this reason, it is imperative for the conventional technique to perform the working of the gate electrode of the memory cell portions in separate from the working of gate electrode of the peripheral circuit transistor portions.
Moreover, since the silicon nitride film can be hardly oxidized, it is conceivable to form the inter-poly insulator film only with the silicon nitride film so as to prevent the degradation of the inter-poly insulator film. However, since the silicon nitride film formed by means of the LPCVD method is prone to generate a lot of leak current, problems may be raised if the silicon nitride film is employed as it is as an inter-poly insulator film.